Electrodeposition Systems
Electroplated Cu Pillar Feature Effects, by R. Hollman, J. Zhang, Z. Liu, A. Keigler presented at iMAPS Device Packaging Conference, March 2010
Introducing NEXX-Section™ for improved via filling analysis
As seen online in Advanced Packaging
Optimized TSV Filling Processes Reduce Costs, by Arthur Keigler, Zhen Liu, and Johannes Chiu, Semiconductor International, May 2009.
Enabling 3-D Design, by A. Keigler, K. O'Donnell, Z. Liu, B. Wu, J. Trezza, Semiconductor International, August 2007.
Reaction Engineering of Through-Chip Via Filling for Wafer-Level 3D Packaging, by D.P. Barkey, J. Callahan, A. Keigler, Z. Liu, A. Ruff, J.. Trezza, and B. Wu, presented at ECTC 2007. Presentation made at ECTC 2007.
Pattern Effects on Electroplated Copper Pillars, by A. Keigler, B. Wu, J. Zhang, Z. Liu, presented at IWLPC November 2006.
Copper Deposition for Pillars and Vias Semiconductor Manufacturing, August 2006.
Active Boundary Layer Thinning in Advanced Packaging Electroplating Semiconductor International, June 2006.
Advances in Metal Deposition for Wafer Bumping by Matt Dorogi, Mark Welsh, and Arthur Keigler, from Advanced Packaging, 2/06 [500k]
Diffusion Boundary Layer Studies in an Industrial Wafer Plating Cell Journal of The Electrochemical Society, 152 (5) (2005)
Stratus Datasheet 7/08
