THE STRATUS Electrochemical Deposition System

Nexx Systems

The Stratus Electrochemical Deposition System


The leader in advanced wafer-level packaging

The Stratus is a fully automated electrochemical deposition system for advanced wafer level packaging applications. The Stratus deposits thick metal layers for wafer bumping, redistribution layers, TSVs, integrated passives, and MEMS. Our unique technology and architecture enables flexible, low-cost and high yield processes.

The Stratus operates with the wafers in a vertical position. The vertical orientation facilitates higher quality processing and a unique modular architecture. And the modularity enables concurrent processing that increases efficiency and throughput.

No other electrochemical deposition tool combines the deposition quality and process advantages of vertical orientation, with the economic advantages of concurrent processing.

Vertical wafer orientation exampleVertical wafer orientation

The Stratus is the ideal choice for the most demanding applications such as through silicon via (TSV) processes, lead free bumping, copper pillars and much more.

Low capital costs, low chemical use, and a small footprint add up to the lowest cost of ownership for any electrochemical deposition system. The Stratus is the most cost-effective ECD tool on the market.

A modular architecture
The Stratus modular architecture enables multiple configurations within a small footprint.

Illustration of Stratus' modular architectureModular architecture Two-wafers are positioned back-to-back in an 8-inch wide process cell. The narrow cell width fits more processes in less space. Stratus offers multiple metals with independently controlled process chemistries in each reservoir. The system can be configured with up to 20 wafer plating positions, providing extreme flexibility. That’s two to three times the capacity of a fountain system.

This configuration, combined with sufficient rinse/dry and pretreatment capacity, provides more than twice the throughput of competing tools. The Stratus' modular architecture optimizes your ECD process – with the smoothest transition from R&D to multi-metal, high-volume production
Worker operating the Stratus machinery The result, is that Stratus provides the most consistent deposition across the entire wafer surface - even with 300mm wafers.




Cu Pillar Features

Electroplated Copper Pillar Feature Effects
by Jim Zhang, Richard Hollman, Zhenqui Liu and Arthur Kielger
Wafer & Device Packaging and Interconnect, Sept-Oct 2010

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Copper Pillar paper

Copper Pillar Electroplating Process Control for Wafer Level Packaging
by Jim Zhang, Richard Hollman, Zhenqui Liu and Arthur Kielger
Presented at the International Wafer Level Packaging Conference Oct 2010

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Electroplated paper

Electroplated Cu Pillar Feature Effects
by R. Hollman, J. Zhang, Z. Liu, A. Keigler
Presented at iMAPS Device Packaging Conference, March 2010

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NEXX article

Introducing NEXX-Section™
for improved via filling analysis
As seen online in Advanced Packaging

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Optimized Filing paper

Optimized TSV Filling Processes Reduce Costs
by Arthur Keigler, Zhen Liu, and Johannes Chiu

Semiconductor International, May 2009

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Semiconductor 3D Chip

Enabling 3-D Design
by A. Keigler, K. O'Donnell, Z. Liu, B. Wu, J. Trezza
Semiconductor International, Aug 2007

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ECTC paper

Reaction Engineering of Through-Chip Via Filling for Wafer-Level 3D Packaging
by D.P. Barkey, J. Callahan, A. Keigler, Z. Liu, A. Ruff, J.. Trezza, and B. Wu
Presented at ECTC 2007
Presentation made at ECTC 2007

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Pattern Effects paper

Pattern Effects on Electroplated Copper Pillars
by A. Keigler, B. Wu, J. Zhang, Z. Liu
Presented at IWLPC Nov 2006

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Copper Deposition paper

Copper Deposition for Pillars and Vias
Semiconductor Manufacturing, Aug 2006

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Active Boundary Layer

Active Boundary Layer Thinning in Advanced Packaging Electroplating
Semiconductor International, June 2006

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Metal deposition

Advances in Metal Deposition for Wafer Bumping
by Matt Dorogi, Mark Welsh, and Arthur Keigler
>From Advanced Packaging, Feb 2006

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Diffusion Boundary

Diffusion Boundary Layer Studies in an Industrial Wafer Plating Cell
Journal of The Electrochemical Society, 2005

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